1. Field of the Invention
The present invention relates to an inspection device and an inspection method. The present invention particularly relates to an inspection device and inspection method for inspecting operational states of a power-on reset circuit for initializing a logic circuit when a DC voltage is applied.
2. Description of the Related Art
When a DC voltage is applied (when power is turned on) as a power supply voltage to a semiconductor integrated circuit that includes latch circuits, flip-flops and the like, logical values of signals output from the semiconductor integrated circuit may not be stabled. Accordingly, a power-on reset circuit (hereinafter referred to as “PoR circuit”) for consistently providing predetermined values (values that have been reset) as logical values of the signals that are outputted, when the DC voltage is applied, is provided in the semiconductor integrated circuit (for example, see Japanese Patent Application Laid-Open (JP-A) No. 2008-17101). To enhance the reliability of the semiconductor integrated circuit, it is important to inspect whether or not the PoR circuit is functioning normally.
FIG. 5 illustrates an example of a conventional inspection device 50. As illustrated in FIG. 5, the inspection device 50 includes elements that configure a part of a semiconductor integrated circuit 100, a control device 122 and a tester 124. The semiconductor integrated circuit 100 includes a PoR circuit 102, an internal logic circuit 104, a test signal generation circuit 106, a selector circuit 116, an external input terminal 118 and an external output terminal 120. The PoR circuit 102 includes a voltage application terminal 102A, a grounded terminal 102B and an output terminal 102C. The internal logic circuit 104 includes an input terminal 104A and an output terminal 104B. The test signal generation circuit 106 includes an input terminal 106A and an output terminal 106B. The selector circuit 116 is a multiplexer, and includes AND circuits 110 and 112 and an OR circuit 114. A DC voltage VDD is applied to the inspection device 50 and the semiconductor integrated circuit 100 as the power supply voltage.
When the DC voltage VDD is applied to the semiconductor integrated circuit 100, the PoR circuit 102 initializes the internal logic circuit 104 (hereinafter referred to as “resetting”). At the PoR circuit 102, the output terminal 102C is connected to the input terminal 104A of the internal logic circuit 104 via a signal line A. The DC voltage VDD is applied to the voltage application terminal 102A, and a ground voltage (GND) is applied to the grounded terminal 102B. The PoR circuit 102 outputs a low-level reset signal for a period, specified in advance as start-up period of the DC voltage VDD, to reset the internal logic circuit 104. When the rising of the DC voltage VDD has finished, that is, when the period specified in advance has elapsed since application of the DC voltage VDD, the PoR circuit 102 uses the rising of the DC voltage VDD to raise (transit) the signal level of the reset signal from low level to high level, in order to release the reset state of the internal logic circuit 104.
The input terminal 106A of the test signal generation circuit 106 is connected to the external input terminal 118. When the rise of the DC voltage VDD stops, that is, when the period specified in advance as the rise time of the DC voltage VDD has elapsed, the test signal generation circuit 106 outputs a test signal with a predetermined signal level from the output terminal 106B, and fixes the signal level thereof.
The AND circuit 110 of the selector circuit 116 includes a positive logic input terminal 110A, a negative logic input terminal 110B, and an output terminal 110C. The positive logic input terminal 110A is connected to the output terminal 104B of the internal logic circuit 104 via a signal line B. The negative logic input terminal 110B is connected to the output terminal 106B of the test signal generation circuit 106 via a signal line C. The AND circuit 112 of the selector circuit 116 includes positive logic input terminals 112A and 112B, and an output terminal 112C. The positive logic input terminal 112A is connected to the signal line A and the positive logic input terminal 112B is connected to the signal line C. Further, the OR circuit 114 of the selector circuit 116 includes positive logic input terminals 114A and 114B, and an output terminal 114C. The positive logic input terminal 114A is connected to the output terminal 110C of the AND circuit 110, the positive logic input terminal 114B is connected to the output terminal 112C of the AND circuit 112, and the output terminal 114C is connected to the external output terminal 120 via a signal line D. Therefore, in accordance with the test signal outputted from the test signal generation circuit 106, the selector circuit 116 outputs a signal to the external output terminal 120 that has the same level as one of the signals inputted from the internal logic circuit 104 and the signal inputted from the PoR circuit 102.
The control device 122 is connected to the external input terminal 118. The control device 122 controls operation of the semiconductor integrated circuit 100. When the rise of the DC voltage VDD has ended, the control device 122 outputs an instruction signal to the test signal generation circuit 106 via the external input terminal 118 that instructs the start of output of the test signal. In response, the test signal generation circuit 106 generates the test signal with a predetermined signal level, and outputs the test signal through the output terminal 106B.
An input terminal of the tester 124 is connected to the external output terminal 120. From logical values of signals inputted from the selector circuit 116 via the external output terminal 120, the tester 124 inspects whether the PoR circuit 102 is functioning normally.
FIG. 6 illustrates transiting states of signal levels of the signal lines A to D, when the DC voltage VDD is being applied to the inspection device 50 and the semiconductor integrated circuit 100. As illustrated in a timing chart for signal line A in FIG. 6, the PoR circuit 102 starts output of the low-level reset signal when application of the DC voltage VDD is started. In response, the signal level of the signal outputted from the internal logic circuit 104 becomes a high level or a low level, as illustrated by the timing chart for signal line B in FIG. 6. Here, the selector circuit 116 outputs a signal representing the logical sum (OR) of, the logical product (AND) of the signal inputted from the internal logic circuit 104 and the high-level signal to which the low-level signal inputted from the test signal generation circuit 106 is inverted, and the logical product of the reset signal inputted from the PoR circuit 102 and the low-level signal inputted from the test signal generation circuit 106. Note that the timing chart for signal line D in FIG. 6 illustrates an example of the state in which a low-level signal is outputted from the selector circuit 116.
However, as illustrated by the timing chart for signal line A in FIG. 6, when the signal level of the reset signal rises to high level using the rise of the DC voltage VDD, the test signal generation circuit 106 outputs the test signal in response to the instruction from the control device 122 simultaneously with the rise of the reset signal. At this time, the selector circuit 116 outputs a signal representing the logical sum of, the logical product of the signal inputted from the internal logic circuit 104 and the low-level signal to which the high-level test signal inputted from the test signal generation circuit 106 is inverted, and the logical product of the reset release signal inputted from the PoR circuit 102 and the test signal inputted from the test signal generation circuit 106. This signal is a high signal as illustrated for signal line D in FIG. 6.
The tester 124 determines that the PoR circuit 102 is functioning normally if the signal inputted from the semiconductor integrated circuit 100 during the rise of the DC voltage VDD is a low-level signal, and the signal inputted from the semiconductor integrated circuit 100 after the rise time of the DC voltage VDD has elapsed is a high-level signal.
Now, the PoR circuit 102 that is the inspection target circuit is a circuit that includes a P-channel MOS transistor that serves as a resistor (R) and an N-channel MOS transistor that serves as a capacitive element (C). Consequently, because of the time constant of an RC circuit including the P-channel MOS transistor and the N-channel MOS transistor, the signal level of the reset signal has a slow rise in a period before reaching the predetermined level. This slow rise is not preferable when determining whether the PoR circuit 102 is functioning normally from the logical values of the signals outputted from the semiconductor integrated circuit 100. In addition, the time constant of the RC circuit varies with the environments in which individual PoR circuits 102 are disposed, degrees of deterioration over time, or the like. Therefore, it has been difficult to specify when the reset release signal will be outputted, after the DC voltage VDD is applied. Accordingly, in the conventional inspection device, the function of the PoR circuit 102 has been inspected by monitoring signals outputted from the output terminal 114C while raising the voltage value of the DC voltage VDD in steps.
However, the above inspection method may only be used if the rise time of the DC voltage VDD is long (for example, of the order of milliseconds or more), and therefore inspection is difficult if the rise time of the DC voltage VDD is short (the microseconds level) due to the limitations in operation times of the tester 124.